An autonomous AI agent designs CPU architectures end-to-end, from concept to verified, tape-out-ready GDSII—and it just did it in 12 hours. Design Conductor, developed by startup Verkor.io, built a complete RISC-V CPU core called VerCore from a mere 219-word specification document, producing multiple micro-architecture variations without human intervention. This marks the first time an autonomous agent has delivered a working CPU from spec to tape-out layout.
Key Takeaways
- Design Conductor autonomously built VerCore, a complete RISC-V CPU, in 12 hours from a 219-word spec sheet
- VerCore achieves 1.48 GHz timing closure using ASAP7 PDK, just below the 1.6 GHz target
- Comparable human-designed RISC-V CPUs required many tens of billions of tokens—vastly more compute than DC’s process
- VerCore implements a 5-stage pipelined, in-order design supporting RV32I and Zmmul instruction sets
- Verkor is deploying Design Conductor with multiple top fabless companies to accelerate time-to-market
What Design Conductor Actually Does
Design Conductor is an autonomous agent that applies frontier AI models to build semiconductors end-to-end—from initial concept through verified, tape-out-ready GDSII layout files. Rather than requiring human architects to hand-code RTL, debug testbenches, and manually optimize timing closure, DC handles the entire pipeline autonomously. The system implements RTL, builds testbenches, debugs frontend issues, optimizes for timing closure, and interacts directly with backend physical design tools.
What makes this significant is scale and speed. A human design team working on an equivalent RISC-V CPU would have required many tens of billions of tokens worth of compute and coordination time. DC accomplished the same task in 12 hours, fully autonomously, producing silicon-ready layout. The specification document itself was minimal—just 219 words describing hardware interfaces, instruction set requirements, and a 1.6 GHz clock target.
Inside VerCore: The Architecture
VerCore is deliberately simple by modern standards, which is precisely why it serves as a powerful proof-of-concept. The design implements a 5-stage pipelined, in-order, single-issue architecture with a 32-bit datapath. It includes instruction and data caches, synchronous interfaces, and a register file implemented as flip-flops that read anytime during a cycle and write at the next rising clock edge.
The CPU supports RV32I (the base 32-bit RISC-V ISA) and Zmmul (multiplication extension), but does not include compressed instructions. This constraint was intentional—keeping the design scope bounded while still producing a complete, functional core. DC built several micro-architecture variations of VerCore, each meeting the timing requirements, demonstrating that the agent can explore design trade-offs autonomously.
Timing closure was achieved at 1.48 GHz using the ASAP7 process design kit, slightly below the 1.6 GHz target but still a functional, verified result. For performance context, VerCore’s CoreMark score of 3261 is roughly equivalent to an Intel Celeron SU2300 from mid-2011 running at 1.2 GHz. That comparison underscores the simplicity of the design—but also its completeness. This is not a simulation or partial implementation. It is a real, synthesizable, tape-out-ready CPU core.
Why This Matters for Chip Design
The semiconductor industry has long relied on specialized human expertise—architects, RTL engineers, physical designers, and verification specialists working in sequence. Each stage introduces delays. A typical CPU design cycle spans months or years. Design Conductor compresses that timeline dramatically, at least for simpler cores, by automating the entire flow and allowing the AI agent to iterate across architectural variations without waiting for human feedback between stages.
Verkor is already working with multiple top fabless companies to deploy Design Conductor for accelerating time-to-market. For companies designing custom silicon—whether for AI accelerators, edge processors, or specialized compute—faster design cycles directly translate to competitive advantage. An agent that can iterate through architectural trade-offs in hours rather than months reshapes the economics of chip design.
The RISC-V instruction set architecture is particularly well-suited to this workflow. Unlike proprietary ISAs locked into specific vendor ecosystems, RISC-V’s modular, extensible nature allows AI agents to reason about instruction sets, optimize them for specific workloads, and generate hardware that integrates cleanly with software stacks. This flexibility is central to why an autonomous agent can design complete CPUs without human intervention.
Limitations and What Comes Next
VerCore is intentionally simple—a 5-stage pipeline is nowhere near the complexity of modern high-performance processors. Real-world CPUs shipping today include branch prediction, out-of-order execution, speculative execution, multi-level caches, and sophisticated power management. Design Conductor has not yet tackled those complexities. The 12-hour result is a milestone, not a replacement for human expertise on advanced designs.
The research team published their work as an arXiv preprint (2603.08716) in March 2026, making the methodology public. This transparency matters because it invites scrutiny and reproducibility. Skeptics can examine whether DC’s approach truly handles all the constraints of real hardware design or whether the simplicity of VerCore masks limitations that would emerge at higher complexity.
What is clear is that the frontier has moved. An autonomous agent has designed a complete, working CPU from specification to tape-out. The next question is not whether this is possible—it is how fast the complexity ceiling rises. Can DC handle branch prediction? Out-of-order execution? Multi-core designs? If so, the semiconductor industry faces a genuine inflection point in how chips are designed and how quickly design cycles compress.
How does VerCore compare to other simple RISC-V cores?
VerCore is not the only simple RISC-V implementation. Academic and open-source projects like PicoRV32 and other educational cores exist. However, VerCore is the first to be designed entirely autonomously by an AI agent and verified to tape-out readiness. Its CoreMark score of 3261 reflects a straightforward 5-stage design; other simple cores may score differently depending on their pipeline depth and optimization targets. The distinction is not performance—it is the autonomous design process itself.
Can Design Conductor handle more complex chip designs?
The research brief does not detail whether Design Conductor has been tested on more complex architectures like out-of-order execution, branch prediction, or multi-core designs. VerCore is intentionally simple—a proof-of-concept that the agent can handle the full design flow autonomously. Scaling to modern complexity levels remains an open question that future work will address.
Will Design Conductor be available to chip designers outside Verkor?
Verkor is currently deploying Design Conductor with multiple top fabless companies, but no public availability date or pricing has been announced. The arXiv publication suggests the methodology will remain accessible to researchers, but commercial licensing terms and timelines are not yet public.
The semiconductor industry is at an inflection point. For decades, chip design has been a bottleneck—expensive, time-consuming, and gated by scarce human expertise. Design Conductor demonstrates that autonomous AI agents can now handle the full design pipeline end-to-end, at least for simpler cores. Whether this capability scales to the complexity of modern processors remains to be seen, but the trajectory is clear. The era of fully autonomous chip design has begun, and it will force the industry to rethink how it trains engineers, allocates design resources, and competes on time-to-market.
This article was written with AI assistance and editorially reviewed.
Source: Tom's Hardware
