Samsung HBM5 has made its first public appearance as a physical mockup at Computex 2026 in Taipei, and the story is less about raw bandwidth than about heat. HBM5 refers to Samsung’s eighth-generation High Bandwidth Memory, a technology designed to feed the insatiable data appetite of next-generation AI accelerators. The headline feature is not a speed number — it is a new in-package thermal design called the Heat Path Block, or HPB, which Samsung believes could redefine how the industry manages heat inside stacked memory packages.
Key Takeaways
- Samsung showed the first physical HBM5 mockup at Computex 2026 in Taipei, signalling serious development progress.
- The new Heat Path Block (HPB) creates an independent thermal path inside the package to reduce heat buildup in AI chips.
- Samsung CTO Song Jae-hyuk described HPB as a chimney-like structure that lowers thermal resistance.
- HBM5 is planned with a 2nm base die and stack configurations of 12, 16, and 20 DRAM layers.
- Mass production is not expected until around 2028, making this a roadmap signal rather than a near-term product launch.
What Is Samsung HBM5 and Why Does Heat Matter?
Samsung HBM5 is the company’s eighth-generation High Bandwidth Memory, built on an in-house 2nm foundry process for the base die and planned in 12-layer, 16-layer, and 20-layer DRAM stack configurations. At those densities, thermal management stops being a footnote and becomes a fundamental design constraint. The more layers you stack, the harder it is to pull heat out from the dies buried in the middle — and in AI workloads, those dies run hot continuously.
This is precisely why Samsung paired the HBM5 mockup with the Heat Path Block. Rather than relying entirely on external system-level cooling — heatsinks, liquid loops, or vapor chambers attached to the GPU package — HPB creates an independent thermal path inside the HBM package itself. Samsung CTO Song Jae-hyuk described it as a chimney-like structure that lowers thermal resistance by routing heat away from die interfaces before it can accumulate. The concept is elegant: give heat a dedicated escape route inside the package, not just outside it.
How the Heat Path Block Works Inside HBM
The Heat Path Block operates within the D2D PHY region — the Die-to-Die Physical Layer that handles ultra-high-speed data transfer between HBM and external GPUs. This is one of the most thermally stressed zones in the entire package, because it sits at the intersection of high-frequency signalling and dense die stacking. By placing an independent thermal path here, HPB improves heat conduction and dissipation at exactly the point where it is most needed.
Samsung did not deploy HPB straight into HBM5 without testing. The company validated the structure in HBM4E first, treating that generation as a proving ground before committing to full deployment in HBM5. That is a sensible engineering approach — introducing a novel thermal architecture into an unproven generation simultaneously would be a significant risk. The HBM4E validation gives Samsung real-world data on how HPB performs under production conditions before the higher-stakes HBM5 rollout.
At the same event, Samsung also showcased an HBM4E wafer and chipset, reporting a maximum bandwidth of 4 terabytes per second. Samsung also said it plans to apply hybrid copper bonding technology to HBM4E — a process change intended to improve electrical and thermal connectivity between stacked dies.
Samsung HBM5 vs SK Hynix iHBM: Two Philosophies, One Problem
Samsung’s HPB approach is a direct response to competitive pressure from SK hynix, which has unveiled its own thermal strategy called iHBM — a solution that integrates cooling elements directly into the HBM package. Both companies are trying to solve the same problem: AI accelerators are generating more heat than conventional cooling architectures can handle, and the bottleneck is increasingly inside the memory package, not just around it.
The architectural philosophies differ. SK hynix’s iHBM integrates cooling elements as part of the package construction, while Samsung’s HPB focuses on creating a dedicated internal thermal path through the D2D PHY region. Which approach proves more effective in production AI systems will depend on real-world thermal measurements that neither company has published yet. What is clear is that thermal design has become a primary competitive axis in HBM development — not just bandwidth, not just power efficiency, but the ability to keep stacked dies cool under sustained AI workloads.
Samsung’s broader challenge is context. As reported by TechTimes, Nvidia’s endorsement has continued to favour SK hynix in the HBM supply chain. That makes the HBM5 thermal story more than an engineering exercise — it is Samsung’s argument for why its next-generation memory deserves a seat at the table in AI accelerator designs.
When Will Samsung HBM5 Actually Ship?
Mass production for Samsung HBM5 is not expected until around 2028, with volume shipments potentially extending into 2028 to 2029. What Samsung showed at Computex 2026 is a mockup and a roadmap signal, not a product ready for customer qualification. That timeline is worth keeping in mind when evaluating the Heat Path Block claims — HPB has been validated in HBM4E, but its full-scale performance in HBM5 stacks remains to be demonstrated in production conditions.
Is the Heat Path Block a proven technology?
Samsung validated the Heat Path Block thermal structure in HBM4E before planning its full deployment in HBM5. That means HPB has gone through at least one round of real-world testing, but it has not yet been proven at the scale and stack density of HBM5. Production results will be the definitive test.
How does Samsung HBM5 compare to SK hynix’s approach?
Samsung’s HBM5 uses an internal Heat Path Block to create a dedicated thermal route through the D2D PHY region, while SK hynix’s iHBM integrates cooling elements directly into the package structure. Both target the same overheating problem in AI memory, but through different architectural strategies. Neither company has published head-to-head thermal data yet.
When is Samsung HBM5 expected to reach mass production?
Mass production for Samsung HBM5 is expected around 2028, based on current roadmap reporting. The Computex 2026 showing was a physical mockup, not a product ready for commercial shipment. Customers evaluating HBM5 for next-generation AI accelerators should plan around that timeline.
Samsung HBM5 and its Heat Path Block cooling structure represent the company’s clearest statement yet that the next memory war will be fought on thermal grounds, not just bandwidth charts. Whether HPB can close the gap with SK hynix in AI supply chain preferences is a question that 2028 will answer — but showing up at Computex 2026 with a physical mockup and a credible thermal strategy is at least a serious opening move.
Edited by the All Things Geek team.
Source: Tom's Hardware
