AMD’s Helios MI455X platform has emerged as the company’s most ambitious answer to Nvidia’s next-generation rack-scale AI systems, but a critical architectural compromise threatens to undercut its performance advantage before it even ships. The AMD Helios MI455X platform is a rack-scale AI system built around 72 Instinct MI455X accelerators, delivering up to 2.9 FP4 exaFLOPS and 1.4 FP8 exaFLOPS per rack, positioned as AMD’s first complete solution for trillion-parameter training and inference workloads.
Key Takeaways
- Helios packs 72 MI455X accelerators and 31 TB of HBM4 memory into a single rack
- Early systems may rely on UALink-over-Ethernet instead of native UALink fabrics
- Native UALink switching silicon is not expected until late 2026
- HPE will offer Helios worldwide in 2026 using Broadcom-designed Ethernet switches
- Helios targets Nvidia’s Vera Rubin NVL72 but with different architectural tradeoffs
The Ethernet Problem: Temporary Fix or Permanent Liability?
The AMD Helios MI455X platform’s real bottleneck is not compute—it is interconnect. AMD designed Helios around Ultra Accelerator Link (UALink), an open-standard fabric meant to deliver massive bandwidth between accelerators within a rack. But here is the problem: the switching silicon that enables true UALink does not exist yet. To ship systems in 2026, AMD and its partners are resorting to UALink-over-Ethernet, a workaround that AMD’s own documentation describes as “not exactly a way UALink was meant to be used”. This is not a minor engineering detail. Interconnect bandwidth directly determines how efficiently distributed training runs across 72 accelerators. Ethernet tunneling introduces latency and reduces effective throughput compared to purpose-built fabric switching. For workloads that require tight synchronization across dozens of GPUs—exactly the trillion-parameter models Helios targets—this gap matters.
AMD expects UALink switching silicon to arrive in the second half of 2026, at which point Helios systems can transition to native UALink fabrics. Until then, early deployments will operate below their theoretical ceiling. HPE, announced as one of the first OEMs to adopt Helios, will use a purpose-built scale-up Ethernet switch developed with Broadcom to support UALink-over-Ethernet. It is a pragmatic solution, but pragmatism is not the same as optimal.
How Helios Stacks Against Nvidia Vera Rubin
Nvidia’s Vera Rubin NVL72 system represents the direct competitor to Helios. Both pack 72 accelerators into a rack, but they make different architectural bets. Helios delivers 31 TB of HBM4 memory total, exceeding Nvidia’s 20.7 TB in the Vera Rubin, and achieves comparable FP8 training performance at around 230 PFLOPS versus Nvidia’s 180 PFLOPS. Where Vera Rubin dominates is interconnect bandwidth—Nvidia’s system delivers 259 TB/s, roughly 16 times higher than Helios’ estimated 16 TB/s. That bandwidth gap is the inverse of the Helios problem: Nvidia invested in custom switching silicon from day one, while AMD is gambling that ecosystem partners like Astera Labs, Auradine, Enfabrica, and Xconn will deliver UALink switches fast enough to close the gap.
For inference workloads using low-precision formats like FP4, Vera Rubin’s 3.6 exaFLOPS edges out Helios’ 2.9 exaFLOPS. Helios counters by optimizing the MI455X for FP4, FP8, and BF16 precision, making it efficient for the exact inference and training workloads that define modern large language model deployments. The choice between systems depends on whether you value total memory capacity and training efficiency (Helios) or maximum interconnect bandwidth and inference throughput (Vera Rubin).
AMD’s Open-Standard Bet: Advantage or Liability?
AMD frames Helios as an open, full-stack platform designed to work with industry-standard components wherever possible. Scale-out networking uses Pensando Vulcano 800G NICs and Pensando Pollara 400G adapters, both vendor-neutral solutions. This openness is theoretically an advantage—customers are not locked into Nvidia’s proprietary ecosystem. But openness only matters if the ecosystem actually delivers. UALink adoption depends on third-party silicon vendors hitting aggressive timelines. If switching silicon slips into 2027, Helios customers will spend a year operating with Ethernet-constrained bandwidth. If ecosystem partners prioritize Nvidia integrations over AMD, UALink may never reach critical mass.
AMD’s strategy assumes that the open-standards approach will attract enough vendor support to overcome Nvidia’s head start. The company says Helios is “exactly on track to launch” later in 2026, but that timeline assumes UALink switching arrives on schedule and that HPE and other OEMs can scale production quickly. Neither assumption is guaranteed.
When Will Helios Actually Deliver Its Promised Performance?
The AMD Helios MI455X platform’s theoretical performance—up to 3 AI exaflops per rack—assumes full utilization of all 72 accelerators with optimal interconnect efficiency. In practice, early 2026 systems using UALink-over-Ethernet will fall short of that ceiling. The platform’s real performance will depend on three factors: when native UALink switching silicon ships, how aggressively ecosystem partners integrate it, and whether customers are willing to accept interim Ethernet-based systems or wait for the full architecture. AMD’s own roadmap suggests late 2026 for true UALink support, meaning the first year of Helios deployments will operate as a partial solution. That is not a deal-breaker for customers who need GPU capacity now, but it is a meaningful gap between marketing claims and shipping reality.
What Happens If UALink Adoption Stalls?
There is a darker scenario: what if UALink switching silicon does not arrive on schedule, or what if ecosystem partners deprioritize it in favor of Nvidia’s roadmap? AMD has contingency plans. Systems can operate in mesh or torus configurations instead of large-scale fabrics, reducing bandwidth but maintaining basic functionality. This would turn Helios into a capable but not exceptional system—good enough for some workloads, but not the transformative platform AMD is positioning it to be.
FAQ
When will the AMD Helios MI455X platform be available?
HPE will offer Helios worldwide in 2026, with systems expected to launch later that year. Native UALink switching support is targeted for the second half of 2026, meaning early systems will use UALink-over-Ethernet.
How much memory does each Helios rack contain?
Each Helios rack includes 31 TB of HBM4 memory distributed across 72 MI455X accelerators. This exceeds Nvidia Vera Rubin’s 20.7 TB total memory capacity.
Is the AMD Helios MI455X platform better than Nvidia Vera Rubin?
Helios excels in total memory and FP8 training efficiency, while Vera Rubin dominates in interconnect bandwidth and FP4 inference performance. The choice depends on workload priorities—Helios suits memory-intensive training, Vera Rubin suits bandwidth-hungry inference at scale.
AMD’s Helios MI455X platform represents a genuine shift in the AI infrastructure market, breaking Nvidia’s monopoly on rack-scale systems. But the Ethernet bottleneck is a self-inflicted wound. AMD designed an architecture that demands native UALink to perform as advertised, then shipped it with a temporary workaround. That gamble might pay off if ecosystem partners deliver switching silicon on time and customers accept interim performance limitations. If not, Helios risks becoming a cautionary tale about the gap between engineering vision and market reality. The next six months will determine whether AMD’s open-standards bet succeeds or whether Nvidia’s proprietary approach proves too entrenched to displace.
Edited by the All Things Geek team.
Source: Tom's Hardware
