Intel Xeon 6+ Clearwater Forest is Intel’s first server processor to deploy the company’s 18A manufacturing process, marking a critical inflection point in the chipmaker’s data-center strategy. Unveiled at Computex, the processor represents Intel’s most aggressive push yet to reclaim server leadership through manufacturing advantage rather than incremental core counts. At a roundtable with Intel executives Kira Boyko and Tim Wilson, the conversation centered on one uncomfortable reality: getting 18A wafers into volume production for servers is harder than designing the chip itself.
Key Takeaways
- Intel Xeon 6+ uses 12 compute chiplets on 18A, each with 24 Darkmont cores, reaching 288 cores in single-socket configurations
- The processor stacks compute tiles using Foveros Direct 3D and connects I/O and base tiles via EMIB bridges
- Intel dropped hyper-threading from the design, a significant architectural shift for server CPUs
- The chip supports 12 memory channels with DDR5-8000 and 96 PCIe 5.0 lanes, 64 supporting CXL 2.0
- Systems will arrive later this year, but 18A wafer allocation remains the real bottleneck
Intel Xeon 6+ Clearwater Forest’s Radical Architecture
The Intel Xeon 6+ Clearwater Forest is not a monolithic die. Instead, it is a chiplet-based design that distributes compute across 12 separate tiles manufactured on Intel’s latest 18A process, each packing 24 energy-efficient Darkmont cores. Two additional I/O tiles run on Intel 7, while three active base tiles use Intel 3. This heterogeneous approach allows Intel to isolate the densest, most power-hungry compute work on the most advanced node while keeping I/O and control logic on more mature, higher-yield processes.
The stacking strategy matters more than the individual components. Intel uses Foveros Direct 3D to stack the compute tiles vertically and EMIB bridges for lateral connections between tiles. This architecture is not new in concept—chiplet designs have dominated high-end CPUs for years—but deploying it at 18A scale for servers is a manufacturing gamble. Yield is unknown. Volume is constrained. Yet Intel is betting that the power efficiency and core density gains justify the complexity.
The Wafer Allocation Dilemma Intel Cannot Ignore
The roundtable discussion with Boyko and Wilson inevitably circled back to the question everyone in the data-center industry is asking: where will the wafers come from? Intel has limited 18A capacity, and the company is simultaneously pushing PC makers to adopt 18A-based CPUs like Panther Lake and Wildcat Lake or face allocation cuts. That pressure reveals the real constraint—Intel 7 capacity has been redirected toward higher-margin server and industrial customers, leaving consumer CPU makers scrambling.
For Xeon 6+ Clearwater Forest, this creates a bottleneck that no amount of architectural brilliance can solve. The compute tiles demand 18A yields that are still ramping. Early systems will be available later this year, but in limited quantities. Enterprise customers expecting volume will face delays. This is not a supply-chain problem unique to Intel, but it is one Intel cannot easily hide. AMD’s competing Bergamo and Genoa processors, built on older processes, ship in volume today.
Why Intel Dropped Hyper-Threading from Xeon 6+
One of the most striking design choices in Intel Xeon 6+ Clearwater Forest is the removal of hyper-threading, a feature Intel has defended in server CPUs for nearly two decades. The decision signals a philosophical shift: raw core count and power efficiency matter more to data-center workloads than thread-level parallelism on individual cores. With 288 cores available in a single socket, the argument for hyperthreading weakens considerably. A workload that needs more parallelism gets it through additional cores, not through simultaneous multithreading on the same core.
This choice also simplifies the die and potentially improves yields on 18A, where every percentage point of usable silicon translates to cost. Hyper-threading adds complexity, consumes power, and occupies die area. For a processor launching on a bleeding-edge node, eliminating that overhead makes engineering sense, even if it marks a departure from Intel’s traditional server CPU philosophy.
Memory and I/O: Where Xeon 6+ Competes
If the compute tiles are where Intel takes risk, the memory and I/O subsystems are where the company plays it safe. The Xeon 6+ Clearwater Forest supports 12 memory channels with DDR5-8000, matching the density of competing server CPUs. The platform provides 96 PCIe 5.0 lanes, with 64 lanes supporting CXL 2.0, positioning the chip for AI accelerator attachment and memory pooling scenarios that increasingly define modern data centers.
The platform is drop-in compatible with the current Xeon server socket, a crucial detail for data-center operators. No motherboard redesign. No firmware retraining. Just swap the CPU and gain 288 cores. That backward compatibility is Intel’s only real advantage over a forklift upgrade path, and it is a significant one for enterprises locked into existing infrastructure.
Is the Intel Xeon 6+ Clearwater Forest a Server Inflection Point?
The Xeon 6+ Clearwater Forest is undeniably ambitious. Deploying 18A in volume servers before consumer CPUs ship in meaningful numbers is a bet that data-center margins can subsidize process node ramp. It is also a bet that power efficiency and core density matter more to customers than proven manufacturing stability and supply certainty.
Whether that bet pays off depends entirely on execution. If Intel can ramp 18A yields and deliver volume by mid-year, the Xeon 6+ becomes a serious competitive threat to AMD. If wafer allocation remains constrained and early systems suffer yield issues, the processor becomes a marketing story with limited real-world impact. The roundtable did not resolve this tension—it only underscored how much Intel is gambling on a single manufacturing node to revive its server business.
What core count does the Intel Xeon 6+ Clearwater Forest reach?
The Xeon 6+ Clearwater Forest reaches up to 288 cores in single-socket configurations and 576 cores in dual-socket systems, using 12 compute chiplets with 24 Darkmont cores per tile.
When will Intel Xeon 6+ Clearwater Forest systems be available?
Intel says systems based on the Xeon 6+ will be available later this year, though exact availability depends on 18A wafer ramp and yield.
Why did Intel remove hyper-threading from Xeon 6+?
Intel eliminated hyper-threading in favor of higher core counts and improved power efficiency, prioritizing raw parallelism over thread-level multithreading on individual cores. The decision also simplifies the die and potentially improves yields on the advanced 18A process.
The Intel Xeon 6+ Clearwater Forest is a calculated risk disguised as a product launch. Intel is betting the farm on 18A manufacturing, wafer allocation discipline, and data-center customers’ appetite for latest silicon over proven supply chains. The architecture is sound. The ambition is real. Whether Intel can actually deliver the volume it promises remains the only question that matters.
Edited by the All Things Geek team.
Source: Tom's Hardware
