Intel 18A-P Process Node Targets External Chip Makers

Craig Nash
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Craig Nash
AI-powered tech writer covering artificial intelligence, chips, and computing.
7 Min Read
Intel 18A-P Process Node Targets External Chip Makers — AI-generated illustration

Intel 18A-P process node is a performance-optimized variant of Intel’s 18A (1.8nm-class) fabrication process designed to address manufacturing variability and attract external customers. The refinement comes as Intel ramps high-volume manufacturing of its advanced node across North America, positioning itself as the first U.S.-based producer of a 2nm-class technology with gate-all-around transistors and back-side power delivery.

Key Takeaways

  • Intel 18A-P is a refined variant of 18A targeting external chip makers with improved yields and thermal performance
  • Base 18A delivers 25% more performance than Intel 3 at same voltage, or 36% lower power at same frequency
  • RibbonFET gate-all-around transistors and PowerVia back-side power delivery enable 8-10% density gains and 4% performance improvement
  • 18A in risk production now; high-volume manufacturing begins late 2025 for Intel products and mid-2025 for external tape-outs
  • Intel 18A-P addresses process variability with improving yields, generating inbound customer interest

Intel 18A-P Process Node: What Sets It Apart

The Intel 18A-P process node represents a critical refinement of Intel’s foundational 18A technology, tackling the manufacturing challenges that plague latest nodes. The base 18A already delivered substantial gains over Intel 3: 25% better performance at the same 1.1V voltage and complexity, or 36% lower power at identical frequency and voltage on standard Arm core sub-blocks. At lower voltages—0.75V—the node achieves 18% greater performance and 38% lower power versus Intel 3. The 18A-P variant focuses on stabilizing yields and reducing process variability, making the node more attractive to external customers who demand predictable manufacturing windows and consistent results.

What makes Intel 18A-P competitive is its architectural foundation. The node introduces RibbonFET gate-all-around transistors, replacing the FinFET designs of earlier generations. Paired with PowerVia back-side power delivery, this combination delivers measurable density and performance benefits: 8-10% density gains, 12% RC improvement in metal layers, up to 10x lower voltage droop, and 4% performance improvement at the same power consumption. These gains matter for data center and AI chips, where power density directly impacts total cost of ownership.

Process Specifications and Area Scaling

Intel 18A-P achieves 0.72X area scaling relative to Intel 3, translating to roughly 28-30% less die area or a 1.3X density improvement. This density advantage is critical for high-complexity designs. Standard cell heights have been reduced significantly: high-performance libraries dropped from 240 cell heights to 180, while high-density libraries shrank from 210 to 160 cell heights—approximately 25% vertical reduction. SRAM cells shrink to 0.021 µm² on 18A compared to 0.024 µm² on Intel 3.

The thermal conductivity improvement of 50% cited in Intel’s announcement addresses a real pain point for advanced nodes. Higher thermal conductivity helps dissipate heat more efficiently from the silicon, reducing hot spots and enabling more aggressive frequency scaling. Combined with PowerVia’s voltage droop reduction, the Intel 18A-P process node becomes more suitable for sustained high-performance workloads typical in data centers and AI accelerators.

Manufacturing Timeline and Competitive Position

Intel 18A entered risk production and is now ramping toward high-volume manufacturing. For Intel’s own products, HVM begins later in 2025 for Panther Lake client chiplets, with data center products following in early 2026. External customers—the real test of foundry viability—can expect first tape-outs mid-2025, with 18A-P generating inbound interest as yields improve. Producing advanced nodes in North America is a strategic advantage: Intel 18A is the first 2nm-class node manufactured on U.S. soil, addressing geopolitical supply chain concerns that matter to defense contractors and other regulated industries.

Compared to TSMC’s N2 process, Intel 18A offers different trade-offs. Intel 18A potentially delivers higher performance per unit, while TSMC historically achieves higher density and lower power consumption. Direct performance and thermal comparisons require testing at matched design densities—a test that will only come when both nodes reach volume production with real silicon. For now, Intel’s willingness to share detailed specifications and open its fabs to external customers signals confidence in the node’s maturity and competitiveness.

Why External Customers Matter

The shift toward 18A-P and external customer interest reflects Intel’s strategic pivot from a pure chip manufacturer to a foundry. If Intel can attract fabless companies—those designing chips but lacking manufacturing capacity—to 18A, it validates the node’s quality and positions Intel as a credible alternative to TSMC for advanced work. The 9% performance gain and 50% thermal conductivity improvement in 18A-P are Intel’s answer to yield and reliability concerns that deterred early external interest in base 18A. As yields improve and the node stabilizes, external tape-outs should accelerate.

Is Intel 18A-P ready for production chips?

Intel 18A is in risk production with improving yields. High-volume manufacturing for Intel’s own Panther Lake and Water Forest products begins in late 2025 and early 2026, respectively. External customers can tape out mid-2025, making 18A-P the first practical window for non-Intel designs on the node.

How does Intel 18A-P compare to TSMC N2?

Intel 18A potentially offers higher performance, while TSMC N2 historically achieves better density and power efficiency. Both are 2nm-class nodes. Direct comparison requires real silicon at matched design points—something that will only emerge as both nodes reach volume production.

What is PowerVia and why does it matter?

PowerVia is Intel’s back-side power delivery network, delivering power from the substrate beneath the transistor layer rather than from above. This reduces congestion, improves voltage delivery, and enables 8-10% density gains and 4% performance improvement at the same power level—critical for dense AI and data center chips.

The Intel 18A-P process node is not a revolutionary leap—it is a pragmatic refinement of an already-strong foundation. For Intel’s foundry ambitions, it is the difference between a promising technology and a credible business. If 18A-P yields hold and external customers tape out successfully mid-2025, Intel’s path to competing with TSMC for advanced node share becomes real. Until then, it remains a promising specification sheet backed by improving manufacturing data.

This article was written with AI assistance and editorially reviewed.

Source: Tom's Hardware

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AI-powered tech writer covering artificial intelligence, chips, and computing.